Serial binary adder



Aug. 2, 1966 R. G. CROMLEIGH 3,264,458

SERIAL BINARY ADDER Filed April 4, 1963 7 Sheets-Sheet l MEMORY {22 b ZS DELAY 34 b EXCILUSHIVE 24 ACCUMULATOR OR 7 32 23 b EXOLUfilVE OUTPUT 29 OR SIGN PING PONG EXCLUSIVE b TNHIBITOR b F Ig.3

TIME T3 n PULSES n+1 PULSES INPUT WORD FROM MEMORY STA PULSE C lOl CIO3 CI22 CIO2 C|O4 OUTPUT FROM CIOZ 8 C504 ON LINE X I04 OUTPUT WORD OUTPUT NUMBER INVENTOR RALPH G. CROMLEIGH BY TIME T4 T5 T6 T7 Te T9 T0 Tu T12 T13 Tm Z POSITION Po Pl P2 P3 P4 P5 '7 Sheets-Sheet 3 Filed April 4, 1963 B B W E B H B W 1 a T9 Tlo TIME n PULSES n+I PULSES STA PULSE CIOI CIO3

CIO2

CIO4 OUTPUT FROM CIOZ BI CIO4 ON LINE XIO4 INPUT WORD FROM MEMORY Cl|7 CIZO Cl l8 CH9 CH4 C|25 CI23 CIO6 C|O5 CH5 Cl24 OUTPUT WORD M W 9 l l m w lol w I T m m m 000 m 5 I I m m m a :0: H m I o m OM 000 m0 m I 0 M m m m n 0 R E H D 000 M 7 T l n m 0 m n I 0 000 m0 5 Y R4 5% R mm m UQLL m Ac N I P W E m 0 59 6 4 W U 3 MP M MW mwmmmm m o Tnn W W U CCCCCC C C R AM4 F 000 T R U OFXFB P m ETm N UNUX I TIDIIP UTLTE UNUI WOOOL OUTPUTVNUMBER Aug. 2, 1966 Filed April 4, 1963 TIME n PULSES n+1 PULSES INPUT FROM MEMORY INPUT FROM ACCUMULATOR OUTPUT FROM C102 8 C104 ON LINE X104 OUTPUT FROM C108 ON LINE X108 OUTPUT .Fig.8

TIME

n PULSES n+1 PULSES INPUT FROM MEMORY INPUT FROM ACCUMULATOR OUTPUT FROM C102 8 C104 ON LINE X104 OUTPUT FROM C108 ON LINE X108 OUTPUT Fig.9

R. G. CROMLEIGH 3,264,458

SERIAL BINARY ADDER T Sheets-Sheet 5 T4 T5 T6 T7 Te T9 T10 Tu T12 T13 T|4 Tls T16 T|1 la 19 20 21 22 I I I I 1 l 1 l 1 I P0 P1 P2 P3 P4 P5 P6 0 1 O I I O 1 P1 P2 P3 P4 P5 P6 P1 0 1 O 1 0 1 1 P0 P1 P2 P3 P4 P5 Pa O 1 0 1 O O I O 1 1 P1 P2 P5 P4 P5 P6 P1 0 O O I O 1 O l 1 O O I O O O O 1 O O O O O O O O 1 O 1 O O 0 1 O O O O I O O O O l O O O 0 1 O 0 I 1 1 1 I 1 O I O O 1 O I I 1 O O O O O O O O O O I O O I O I I O O O 0 P2 P-l P0 P1 P2 P5 P4 P5 P6 P1 0 1 O I I 1 O I O 0 V OUTPUT NUMBER T4 T5 Te T7 T5 T9 Tlo T|| T|2 T15 T14 T|5 T16 T17 T18 T|9 T20 T21 T22 I I I I I 1 I I 1 1 1 1 1 1 1 1 P0 P1 P2 P3 P4 P5 P6 1 I O I l 0 Pl P2 P3 P4 P5 P6 P1 0 7m O I 1 O 1 1 P0 P1 P2 P3 P4 P5 Pa O I O O I l I O O 0 Pl P2 P5 P4 P5 P6 P1 0 O 0 0 I 1 O 1 1 O O I O O O O I O O O O O 0 O O O O 1 I O O I O O O O I O O O O 1 O O O O 1 O 0 1 I 1 I 1 I l 1 O 0 1 O I 1 1 0 O O O 0 O 0 O O O O I 1 O 1 I I I O O 0 P2 P-I P0 P1 P2 P3 P4 P5 P6 P1 0 I O 1 I I I O O 1 I OUTPUT NUMBER INVENTOR. RALPH G. CROMLEIGH Aug. 2, 1966 Filed April 4, 1963 TIME n PULSES rI-I-I PULSES INPUT FROM MEMORY INPUT FROM ACCUMULATOR OUTPUT FROM CIOZ 8IC|O4 ON LINE XIO4 OUTPUT FROM CIO8 ON LINE XIO8 clos CIO9

CIO6

F, g [0 OUTPUT 7 Sheets-Sheet 6 MEMORY INVEN T4 T5 T7 Ta T9 TIo TII TI2 TIB Tl4 T|5 TIs TI? TIs TIS T20 T2I T22 I l I I I I I I I I I I I I I I l I Po PI P2 P3 P4 P5 P6 0 I I I O l 0 PI P2 P3 P4 P5 P6 P? I I O O I O I Po PI P2 P3 P4 P5 P6 0 I O O O I O I I I PI P2 P3 P4 P5 P6 P1 0 O I I O O I O I O O I O O O I O I O I O O I I O O I O O O O I O O O I O I O I I O O O I O I O I I I O O O I O I I O O O O O O O I O O I O I O I O O O O O O O O I P2 P4 P0 PI P2 P3 P4 P5 P6 P! O I O O I O I O I I V OUTPUT NUMBER STA G OUTPUT TOR.

RALPH G. CROMLEIGH ATTO RN EY Aug. 2, 1966 R. G. CROMLEIGH SERIAL BINARY ADDER Filed April 4, 1963 '7 Sheets-Sheet 7 Fig/4 CL L CH2 Ni ll T3 22' 233. 23 225 227 LAO. LA.

230 222 IN GU96 c1136 ZIN (Tn. I I O 7 2 (3)1 226 INPUT 234 232 I2 228 2 us 223 Fig/3A I INPUTZ:g 0cm! INVENTOR. RALPH G. CROM LE IGH ATTORNEY United States Patent 3,264,458 SERIAL BINARY ADDER Ralph G. Crornleigh, La Canada, Calif., assignor to Burroughs Corporation, Detroit, Mich., a corporation of Michigan Filed Apr. 4, 1963, Ser. No. 270,625 16 Claims. (Cl. 235-176) This invention relates to an algebraic adder and more particularly to a serial algebraic adder which utilizes bistable magnetic storage elements to effect mathematical computations in a novel and efficient manner.

Basic to a digital computer is that portion of the apparatus which performs the addition and subtraction of two binary numbers. It is the heart of the computer, for any mathematical operation whatsoever can be defined in terms of addition and subtraction. Accordingly, it is very desirable that the operation of the algebraic adder unit of a digital computer be reliable over a long period of time. Such reliability may be achieved by the use of a minimum number of highly reliable circuit elements such as bistable magnetic cores. Greater reliability may be achieved by the use of a serial adder instead of a parallel adder. A parallel adder requires a logic circuit for each so called number bit because each bit of the number occurs simultaneously in time. However, a serial adder requires only one logic circuit because the bits of a serial number occur successively in time. By minimizing the number of logic circuits required, the serial adder is more reliable than the parallel adder. The number of elements included in the serial adder may be reduced, thereby increasing its reliability, by utilizing the same elements for more than one function performed by the adder.

It is a general object of the present invention to provide an improved serial algebraic adder that utilizes bistable magnetic storage elements.

A more specific object of this invention is an improved serial algebraic adder that utilizes a minimum number of bistable magnetic storage elements.

Another object of this invention is an improved serial algebraic adder wherein time and equipment is minimized by overlapping the various functions performed by the adder and, with each circuit within the adder corresponding to a logical function, overlapping the circuits within the adder corresponding to the overlapping functions.

A further object of this invention is an improved serial algebraic adder that gives the sign value of the resulting output number.

A still further object of this invention is an improved serial algebraic adder that rounds off the resulting output number.

These and other objects, are achieved, in accordance with the present invention by utilizing magnetic core sign determining means that senses the sign of a number being serially placed into an algebraic adder unit from a first signal storage device such as a rotating magnetic drum. Once the sign of the incoming number has been determined, the sign determining means may be utilized to trigger a magnetic core shift register of the recirculating or end around type having a one-bit capacity. This device is analogous to the bistable or flip-flop circuits used in voltage level processing systems. It is often called, and is hereinafter referred to as, a ping-pong circuit. When the ping-pong circuit is triggered, it produces a series of pulses that occur simultaneously in time with the serial bits of the number arriving from the first signal storage means. Whether the ping-pong circuit is triggered by the sign determining means depends upon the function the adder is to perform, i.e., substraction or addition, and whether the incoming number from the first signal storage device is positive or negative.

The serial number from the first signal storage device is "ice applied to a first input terminal of a first magnetic core EXCLUSIVE OR circuit and the output of the ping-pong circuit is applied to a second input terminal of the first EXCLUSIVE OR circuit. If the ping-pong circuit was triggered by the sign determining means, the output of the first EXCLUSIVE OR circuit is the ONEs complement of the number applied to the first input terminal of the first EXCLUSIVE OR circuit from the first signal storage device. If the ping-pong circuit was not triggered by the sign determining means, the first EXCLUSIVE OR circuit complements all of the least significant bits of the incoming number from the first signal storage device that are ZEROs prior to the first least significant ONE bit, and the first least significant ONE bit is also complemented. Thereafter, the remaining bits of the incoming number are unchanged by the first EXCLUSIVE OR circuit.

The number to be added to, or subtracted from, i.e., the number arriving from the first signal storage device is serially applied to a second input terminal of a second EXCLUSIVE OR circuit and arrives from a second signal storage device such as an accumulator. The output of the first EXCLUSIVE OR circuit is applied to the first input terminal of the second EXCLUSIVE OR circuit. The bits of the number arriving on the second input terminal of the second EXCLUSIVE OR circuit occur simultaneously in time with the corresponding bits arriving on the first input terminal of the second EXCLUSIVE OR circuit from the first EXCLUSIVE OR circuit.

The output of the first EXCLUSIVE OR circuit is also coupled, through delay means, to a second input terminal of a third EXCLUSIVE OR circuit and the output of the second EXCLUSIVE OR circuit is applied to a first input terminal of the third EXCLUSIVE OR circuit. The out put of the algebraic adder is the output of the third EX- CLUSIVE OR circuit. The delay means and the second and third EXCLUSIVE OR circuits function essentially as a full adder by adding the output of the first EXCLU- SIVE OR circuit to the number applied to the algebraic adder from the second signal storage device.

If the result of the addition or subtraction performed by the algebraic adder is positive, the answer obtained from the output of the third EXCLUSIVE OR circuit is in absolute form. If the result is negative, the answer will appear on the output of the third EXCLUSIVE OR circuit in TWOs complement form.

A sign position bit is also part of the output of the algebraic adder and it indicates whether the sign of the answer number is negative or positive. Whether the sign position bit indicates that the answer number is positive or negative is a function of (a) whether the ping-pong was turned on, (b) the sign of the number supplied by the second sign-a1 storage means, and (c) the internal condition of the third EXCLUSIVE OR circuit at the time the sign position bit is generated.

A more detailed description follows with the accompanying drawings and claims in which:

FIG. 1 is a block diagram of a serial algebraic adder comprising a preferred embodiment of the present invention;

FIG. 1A is a symbolic representation of a sample num- 1bzeirG that is applied to one input of the algebraic adder of FIG. 2 is a symbolic schematic diagram of the serial algebraic adder of FIG. 1;

FIGS. 3, 4, 5, 6, 7, 8, 9 and 10 depict in tabular form the magnetic remanent state of cores in the algebraic adder of FIG. 2 for each time step in certain functions performed by the adder;

FIGS. 11 and 11A show in symbolic and schematic diagram form, respectively, an inhibitor circuit used in the algebraic adder of FIGS. 1 and 2;

FIGS. 12 and 12A show in symbolic and schematic acetates FIGS. l'4-and 14A show in symbolic and schematic dia-. gram form, respectively, another EXCLUSIVE OR-circuit:

usedin the algebraic adder of FIGS. 1 and 2.

Basically, the present invention may be describedas an algebraic adder used in conjunction with an accumulator loop.

The algebraic adder is a serial type full adder that.

forms the sum or difference of two data words in binary coded form. One of the data words is in absolute value form with'its sign value preceding the least significant digit, and a zero following the most significant digit. The other word is in .twos complement form with all of its digit positions being significantup to the signposition which.

follows the most significant digit. The adder produces the sum or difiference of the above mentioned words in the form of a serial output in twos complement form 'with' all digit positions significant up to the sign position which follows the most significant digit. This property permits the adder to be used in conjunction with the accumulator loop which serves both as a receiver of the adder output and as one of the inputs to the adder.

Binary arithmetic considerations show that the correct sum (in twos complement form with a sign following the most significant digit) will result from the addition of anycombination of positive and negative numbers, so long as those numbers are in the same twos complement form.-

The sign is equal to one if the number is negative and zero if positive. Since the one input to the adding circuit coming from the output of the accumulator loop is already in the twos complement form, it only remains to convert the other input word to the algebraic added into its twos complement form.

It is a well known arithmetic exercise to show that subtraction is identical to addition except that the value of the sign of the subtrahend should be negated (changed) before the two numbers are added.

The twos complementing algorithms for binary coded words are as follows: If the word is positive do not change its form except to place a zero after the most significant digit; If the word is negative destroy the sign (which in the absolute value form of the word is in the position preceding the least significant digit),-then leaveall digit values unchanged from the least significant digit position up to and including the occurrence of the least significant ONE. Thereafter the negation of all digit values is formed,.and a ONE placed in the twos complement form sign position (which follows the most significant digit). This operation is herein called modification, rather than,

complementing, since the twos complement form of a posi- 'tive absolute word is identical to itself.

Reference to FIG. 1 which is a block diagram of the serial algebraic adder shows that the adder comprises a first EXCLUSIVE OR circuit 21,.21 second EXCLUSIVE OR circuit 23, a third EXCLUSIVE OR circuit 24, a fourth.

EXCLUSIVE ORcircuit 26, delay means 22, an inhibitor circuit 25, and a ping-pong circuit 27. Each EXCLU- SIVE OR circuit has a first (a) and a second (b) input terminal and a single output. The inhibitor circuit also has a first (a) and a second (b) input terminal and a single output (c). The delay means 22 and the ping-pong circuit 27 has a singleinput and output. Both the first and third EXCLUSIVE OR circuits 21 and 24 respectively contain feedback from within the OR circuit to'the second (b) input terminal.

The first input terminal (a) of the first EXCLUSIVE ORcircuit 21 is coupled to a first source 28 of serial binary information i.e. numbers andto a source of STA pulses.

An STA (start) pulse is generated for each number sups plied by the first source 28. The source 28 of serial bit nary numbers is a memory device such as a rotating mag- 4: netic drum. The serial binary number. from the memory 28 is also applied to the second (b)- input terminal-of the inhibitor 25! The STA pulse source 30 :is'also coupled to the second (b) input terminal of the first EXCLUSIVE OR circuit 21, the second (b) input terminal of the third EXCLUSIVE OR circuit 241,;and the first (a) input termi-v nal of the inhibitor circuit 25. v

The output of the inhibitor circuit 25' is coupled to the second (b) input terminal of the fourth EXCLUSIVE OR circuit 26 and the first (a) input terminal of the fourth EXCLUSIVE OR circuit 26 is coupled to a source of SUA I pulses 31. An-SUA (subtract) pulse is generated whenever the adder is to perform' subtraction. The output of the fourth EXCLUSIVE OR circuit 26 islapplied as an input to the ping-pong circuit 27 and the: output of the ping. pong circuit 27 is applied to the second (b) input terminal of the firstEXCLUSIV-E OR circuit 21 The output of the firstEXCLUSIVE OR circuit 21 is applied to the first, (a) input terminal of the second EX- CLUSIVE ORcircuit 23. 'andis also delayed by the delay means 22 before it enters the second (b) input terminal of the third EXCLUSIVEORcircuit 24. The first (a) input terminal of the second EXCLUSIVE ORcircuit 23 is coupled to a second source 29. of serial binary informa- Such as an 'EICCIIHIUIQIOI.

put of the adder and appears on line 32..

The operation of the. second and fourth EXCLUSIVE OR circuits 23; and .26 are such that whenevera ONE'bit (which is the presence of a pulse) is present on'either the first (a) or second (b) input terminal, 2; ONE is produced on the output of the EXCLUSIVE OR circuit. Whenever a ONE pulseis presenton both the first (a) and'second (b) input terminals, 2. ZERO (which is the absence of a pulse) appears onsthe output of, the EXCLUSIVE OR circuit. When 'aZERO is present on both of the input terminals (:1) and (b) a ZERO is produced on' the output of the EXCLUSIVE OR circuit; The operation of the first and third EXCLUSIVE OR circuits 21 and24 are substantially the same except thatth'e feedback lines 34' and 35 will feedback a ONE pulse. to the second (b) input terminal of the first and third-EXCLUSIVE OR circuits 21 and 24 for the case of a ZERO having been applied to the first (a) input terminal and a ONE having been ap-' plied to the second (b) input terminal. -For all other possible combinations of inputs there is no feedback.

- The operation of the inhibitor circuit 25 is; such that the presence of a ONE on the second (b) input terminal J of the inhibitor'willinhibit, i.e., prevent, the passage: of v a ONE through theinhibitor 25;?that appears on the first (a) input terminal. Therefo're,-a ONE will appear on the output of the inhibitor 25 only'when a ONE is present on the first (a) input terminaland a ZERO'on the second (b) input terminal. For all other possible input .combinations to the inhibitor 25.; a ZERO appears as the output of the circuit. For example, when a ONE is applied to the second (b) input terminal anda ZERO is I applied tothe first (a) inputterminal, a ZERO appears as the output of the circuit because the ONE on the second (b) input terminal only inhibits a ONE .Onthe first (a): input terminal.

The operation of the ping-pong circuit. 27 is such that whenever it receives a triggering ONE-pulse from the fourth EXCLUSIVEVOR circuit- 26; it will. produce a series of ONE pulses that occur simultaneously in time with the. bits of the serial binarynum'ber arriving from the memory unit 28; The ping-pong27 will continue to generate the ONE jpulses until 'it is turned off. There is no output fromthe ping-pong circuit 27 untilit is triggered by a ONE pulse from the fourth EXCLUSIVE OR circuit 26.

The operation of the delay means-22h such that it i will delay any bit applied to it for a sufiicient length of time to permit a carry operation to take place.

FIG. 1A shows in symbolic form an illustrative example of a serial binary number that is placed into the adder by the memory unit 28. Reference to FIG. 1A will show that the number is made up of ONEs, that are the presence of a pulse and ZEROs that are the absence of a pulse. The individual ONEs and ZEROs of the binary number are called bits. Each bit of the number occurs at an even numbered pulse time, i.e., at time T T T etc. The first bit to arrive from the memory 28 is the P position bit which occurs at time T The P bit indicates whether the serial binary number arriving from the memory 28 is negative or positive. If the P bit is a ONE, the number has a negative sign and if the P bit is a ZERO, the number has a positive sign. The next bit to arrive is the P bit which occurs at time T 6 and is the least significant bit of the number arriving from the memory 28. The most significant bit of the number arrives last and occurs at time T Therefore, the number shown in FIG. 1A would appear in absolute value form as:

P P5 P Pa P2 P1 The number is less than unity because the adder is not designed to properly handle an incoming number, or a result of addition or substraction, that is equal to or greater than unity. This in no way limits the capability of the adder for incoming numbers can be scaled down and the output of the adder correspondingly scaled up. The number shown in FIG. 1A contains five bits, excluding the P sign position bit. The adder is not limited to a binary number containing this amount of bits but is capable handling a serial binary number containing any number of bits.

The number to be added to, or substracted from the number arriving from the memory 28 is supplied by the accumulator 29 and is in serial binary form. As will be shown herein below, the binary number arriving from the accumulator 29 does not have its sign indicating bit in the P bit position. It occurs after the most significant bit position, in what would be the P bit position occurring at time T (not shown) of FIG. 1A.

The inhibitor 25 circuit and the fourth EXCLUSIVE OR circuit 26 will determine the sign of the number that is placed into the adder from the memory 28 and, depending upon whether the adder is to pass a single number from the memory 28, perform addition or subtraction, in ping-pong circuit 27 may, or may not, receive a trigger pulse from the fourth EXCLUSIVE OR circuit 26 and be turned on. If the ping-pong circuit 27 is triggered, the output of the first EXCLUSIVE OR circuit 21 will be the ONEs complement of the number supplied by the memory 28. On the other hand, if the pingpong circuit 27 is not triggered, the first EXCLUSIVE OR circuit 21 will complement the least significant bits of the number arriving from the memory 28 that are ZEROs prior to the first least significant ONE bit, and also the first least significant ONE bit. Therefore, the remaining bits of the number will pass through the first EXCLUSIVE OR circuit unchanged. That is, the least significant ONE bit and all lower order ZEROs of the number are ONEs complemented if the number is negative.

The output of the first EXCLUSIVE OR circuit 21 will be added to a number arriving from the accumulator 29 in a circuit comprising the delay means 22, the second EXCLUSIVE OR circuit 23, and the third EXCLUSIVE OR circuit 24. The result of the addition will appear on lead 32, which is the output of the third EXCLUSIVE OR 24 circuit, in serial binary form and will contain a sign position bit that indicates the sign of the result. The sign position bit will be a ONE if the result is negative and a- ZERO if-it is positive. If the result is negative, the

answer number will appear in TWOs complement form. The sign position bit is generated by the third EXCLU- SIVE OR circuit 24 and is determined by the input to the first (a) input terminal of the third EXCLUSIVE OR circuit 24 from the second EXCLUSIVE OR circuit 23 (which, in turn, is determined by whether the pingpong 27 is running and the sign of the word arriving from the accumulator 29) and by the input to the second (b) input terminal of the third EXCLUSIVE OR circuit 24 from the delay means 22, or the feedback on line 35.

Detailed description FIG. 2 is a symbolic schematic diagram of the serial algebraic adder shown in FIG. 1 in block diagram form. The circles in FIG. 2 represent magnetic cores having a substantially rectangular hysteresis loop and having two stable remanent states indicated as a ONE and a ZERO, respectively. A line with an arrow pointing toward a circle represents an input to the core which sets it to the binary state (1 or 0) indicated just inside the circle directly opposite the arrowhead. A double arrowhead indicates that the existence of an input on that line will hold the core to that state despite the presence of other input signals.

Lines originating at a circle containing an arrowhead pointing away from the circle represent output circuits. A signal is present on the output line when the core is switched to the binary state shown nearest the line inside the circle. When an output may only be produced by one of several inputs, a curved line segment is drawn inside the circle from that input to the output such as is shown in cores C and C The symbols used in FIG. 2 are described in detail in the February 1956 issue of the Proceedings of the I.R.E. pages 154 to 162.

The first EXCLUSIVE OR circuit 21 of FIG. 1 comprises COTES C101, C102, C103, C104 and C122, the SCCOlld EXCLUSIVE OR circuit 23 comprises cores C C C and C the third EXCLUSIVE OR circuit 24 comprises cores C C C and C and fourth EXCLUSIVE OR circuit 26 comprises cores C C C and C The inhibitor circuit 25 shown in FIG. 1 comprises cores C and C and C The pingpong circuit 27 shown in FIG. 1 comprises cores C and C Cores C and C function to delay the number arriving from the accumulator 29 so that its bits occur simultaneously in time with the corresponding bits of the number from the memory 28 seen on line X after passing through the first EXCLUSIVE OR circuit 21.

Reference to FIG. 2 will show that each core is advanced by a winding to which either an n pulse or an (n+1) pulse is applied. An n pulse occurs at even pulse times such as times T T T etc. and an (n+1) pulse occurs at odd pulse times such as times T T T etc.

Sign determination Consider now the case of a single binary number arriving from the memory 28 to be passed through the adder. The adder must first determine the sign of the incoming number. Suppose the sign position bit P is a ZERO, indicating the number is positive, and arrives from the memory at time T Prior to the arrival of the P sign bit, all of the cores of the adder will have been placed into the ZERO state.

FIG. 3 shows in tabular form a single positive word input from the memory 28. Referring now to FIGS. 2 and 3, when the P bit arrives from the memory 28 at time T it will be carried on line X to the core C Since P is a ZERO (indicating the number is positive), core C will remain in the ZERO state. Also at time T an STA pulse occurs at terminal 30 which is applied to core C and sets that core into the ONE state.

When the next (n+1) pulse occurs at time T the ONE in core C will be transferred to core C This transfer is not inhibited by core C because a ZERO was in core C at time T At time T the n pulse applied to core C will transfer the ONE from core C into core C and at time Tr} the (n+1) pulse applied to core C will transfer the ONE from core C into core C Then at time T the n pulse appliedto core C will transfer the ONE into core C Cores C and C are connected in a ping-pongconfiguration. At time T core C is set as described, and at time T n pulse applied to core C advances this ONE set as-an output pulse on line X to core C and also sets core C At time T the ONE set of core C isreturned to core C 'by the next (n+1) pulse and the action described above continues, giving output pulses from the sign ping-pong during even pulse times starting with time T and ending when the ping-pong circuit is turned off. Core C C and C can be ignored, for as will be shown below, they only influence the turning on, or not turning on, of the ping-pong circuit when the adder is to perform subtraction.

Assume that the word'arriving tom the memory 28 is negative. Then the P sign position bit will be a ONE. At time T, a ONE will be placed into core C by the P bit and the .STA pulse will place core C into the ONE state. At time T core C will not be set into the ONE state because the ONE being advanced out of core-C is inhibited by the ONE in core C Since a ONE is'not set in core C a ONEwill not be advanced into core C and the ping-pong will not be started.

-Therefore, it has been shown that if P is ZERO (a positive number) the ping-pong will be started and if:

P is ONE (a negative number) the ping-pong will not be activated. The sign of the incoming word has been determined as the activation ofthe ping-pong (cores- C and C going on if the number is positive, and oh if the word is negative.

Passihrough of a single number The number shown in FIG. 3 arriving from the memory 28 would be written in absolute value form as:

.1 0 1 0 1 1 As'explained above, the firstsbit P to arrive from the memory 28 after the sign position bit P is the leastsignificant bit of the number. for this number.) arrives last at time T for the number shown in FIG. 3.

Referring again to FIGS. 2 and 3, when the P sign bit is applied to core C ,it is also applied by way of line X to core C 5 which, with cores C C C and C comprise the first EXCLUSIVE OR circuit 21. The bits of the incoming word occur at even numbered pulse times, i.e., the P bit at time T the P bit at time T etc. pong goes to core C by way of line X and that the sign ping-pong will be turned on at time T because the incoming word is positive, i.e., the P bit is a ZERO.

At time T P is applied into core C The STA pulse also occurs at time T and is applied to core C by line X Since P is a ZERO (the absence of a pulse) and the presence of an STA pulse on line X sets core C into the ZERO state,-core C will remain in a ZERO state. At the same time, the STA pulse also sets core C to the ONE state. The next (n+1) pulse at time. T advances cores C and C thereby EX- CLUSIVE ORing their contents which results in a ONE being set into cores C and C and aZERO inscore- C At time T the next It pulse causes the ONE in core C to be read out and it appears on line X as the output of the first EXCLUSIVE OR circuit 21 corresponding to the P bit position. Also at time T the P bit, which is 21 ONE, enters'core C and the ONE in core C is placed to core C by way of lead 34.

The most significant bit (P Notice again that the outputfrom the sign ping- FIGURE 3 shows that the STA pulse occurs only one, at

' to the ONE state.

eration is such that a ONE will be set into core .Ci and thereafter sent back into core C when and only when a ONE appeared in coreC and a ZERO in core C time T the next 11 pulse will read out: the ZERO 'in cores C and C 5 and it will appear on line X as a' ZERO corresponding to the P bit position. The outputs' of cores C and C are tied togetherarid appear online the next (n+1) pulse occurs at'timeT the ONEin core C is EXCLUSIVEZORed against the ONE in core C 5 which results 'in ZEROs in coresC C and C At time T the ZEROs in cores C1 and C 6 are read out by the next n pulse .and appear on output line X as -a ZERO corresponding to the P bit position.

At time T the P bit which is a'ZERO (absence of a pulse) arrives at core C1 causing core Cm to remain in the. ZERO state into which it was set when the ONE it contained was read out at time T9. The; sign ping-pong, applies a ONE to core C at time .T setting that core.

into the ONE state. When the next; (n+1) pulse occurs at time T the ZERO in core C 5 isiEXCLUSIVE ORed againstthe ONE in coreC which results in a ONE being set into cores C 5 and C and a ZERO in, core C At time T the next n pulse willread out cores C and C producing-a ONE on :the output line X corresponding to the P, bit position. The 11 pulse, occurring at time T will also transfer the ONE in .core C into: core C which coincides with the pulsearriving from the ping-pong which also sets core C into the.

ONE state. Duer to the action of the ping pong, a ONE Will always be set into core C1 starting. at time T Also at time T the P bit which is a ONE arrives at core C setting that core into the ONE state; At time T the ONE incore C willbe EXCLUSIVE ORed with the ONE in core C resulting in ZEROs in cores.

C C and C1 which at timeT will'appear on the output line X as a ZERO corresponding to the P bit. Attime T 4, the P bit, which is a ZERO, isapplied to core C keeping that core in'the ZERO state; Attime T the ZERO in core C will be EXCLUSIVEfORed against the ONE-that was set into core C at time T by a pulse from the ping-pong 27 circuit; The result of: the EXCLUSIVE ORing is to seta ONE in cores C and C and a ZERO in core C which the next (n+1) pulse, occurring at time T1 will read out and which will appear on lineX as a ONE corresponding to the;P bit' position. Also at time T the ONE in core C 'is transferred to .core C together with the pulsef-rom'the pingpong circuit to set that core into the ONE state.

Attime T 5, the P bit; which is 21 ONE also arrives at core C and sets that core into the ONE state. .At time T the ONE: in core C will be EXCLUSIVE ORed against the ONE in core C which results il'l ZERO S being. placed in cores C1 C and C At time T the ZEROs in cores C and C are transferred by the next (n+1) pulse to the output line X where they appear as a ZERO corresponding to the Pg bit'position.

The P bit,'which is the most significant'bit of the num- 1 her, is the last bit of the'number to arrive from the.

memory 28. J Thereafter, therewill' be no more bits arriving from the memory 28 until it supplies the next number to be operated upon by the. adder. .Since' a ZERO is the absence ofa pulse, the memory ZS' afterthe-P' bit has passed, will in effect be supplying a series of ZEROs to core C However, the ping-pong will remain running which will keep core C in the ONE state. The successive EXCLUSIVE ORing of a ZERO in core C and a ONE in core C will produce a series of ONE pulses on the output line X after the passage of the P bit as is shown in FIG. 3.

The P sign position bit occurs on line X as a ONE and occurs at time T i.e., is displaced two pulse times. The number arrived from the memory 28 as:

P0 P1 P2 P3 P4 P5 Pa 0 1 1 0 1 0 1 and appears on line X displaced two pulse times as:

P0 P1 P2 P3 P4 P5 Pa which is the ONEs complement of the input number. That is, the output of the first EXCLUSIVE OR ci-rcult 21 I is the ONEs complement of the input number when the sign of the input number is positive (P is a ZERO).

At time T when the STA pulse was applied to cores C C and C the STA pulse was also applied to core C by way of line X and set that core into the ONE state. The core C together with cores C C C and C comprise the third EXCLUSIVE OR circuit 24. At time T the ONE in core C was EXCLU- SIVE ORed with a ZERO in cores C and C The core C will always contain a ZERO for the case under consideration because there is no input from the accumulator 29. The core C will always contain a ZERO until the arrival of the P bit from the first EXCLUSIVE OR circuit 21 which, as shown above, occurs at time T Therefore, the result of the EXCLUSIVE ORing will be to transfer a ONE to cores C and C and a ZERO to core C At time T the next It pulse will transfer the ONE in core C to line X which is the output of the adder and it will appear on the output terminal 32 as a ONE. This ONE appearing on the output line X at time T corresponds to the P bit position as is shown by FIG. 3. At time T when the number is just starting to arrive from the memory 28, all of the cores contain a ZERO and the n transfer pulse applied to cores C and C at time T; will produce a ZERO on the output line X at time T as shown in FIG. 3, which corresponds to the P bit position.

At time T when the ONE in core C is being transferred to the output line X the ONE in core C is transferred by way of lead 35 to core C and sets that core into the ONE state. The core C and lead 35 comprise a feedback circuit that operates in the same manner as the feedback arrangement discussed above in relation to the first EXCLUSIVE OR circuit 21.

Also at time T the P bit which, as shown above, is a ONE arrives on line X from the first EXCLUSIVE OR circuit 21 and is set into the cores C and C The core C together with cores C C and C comprise the second EXCLUSIVE OR circuit 23. Since there is no input to the second EXCLUSIVE OR circuit from the accumulator 29, the cores C C and C can be ignored and the information arriving from the first EX- CLUSIVE OR circuit 21 will pass through oore C unchanged. The core C together with the core C comprise the delay means 22 shown in FIG. 1.

The next (n+1) pulse at time T; will read out cores C C and C The ONE in core C will be transferred to core C and the ONE in core C will be EXCLUSIVE ORed with the ONE in core C which will result in a ZERO set in cores C C and C The next n pulse at time T will transfer the ZERO in cores C and C to the output line X where it will appear as a ZERO corresponding to the P bit position. Because core C is in the ZERO state at time T it cannot set the core C into the ONE state, however, at time T the ONE in core C is transferred to core C and sets that core into the ONE state. Also'at time T the P bit,

1G which is a ZERO, arrives from the first EXCLUSIVE OR circuit 21 on line X and is applied to cores C and C causing these cores to remain in the ZERO state.

From the above, it is seen that the cores C and C produce a two pulse delay so that every bit placed into core C from line X is delayed two pulse times by the cores C and C and is set into core C at the same time the next occurring bit is set into core C That is, when a bit position is being transferred from the first EXCLUSIVE OR circuit 21 into the core C the last previously occurring bit position is being transferred from core C to core C This does not mean that every bit placed into core C is EXCLUSIVE ORed against the previous bit which is set into core C from core C for the previous bit may be a ZERO set in core C at the same time that a ONE is set in core C The next 11 pulse would tend to transfer both the ZERO in core C and the ONE in core C into the core C which would result in the ONE being set in core C and not the ZERO which was the previously bit stored in core C At time T the ZERO in core C is EXCLUSIVE ORed against the ONE in core C which results in a ONE set in cores C and C and a ZERO set in core C Since a ZERO was the set of core C at time T the set of core C remains a ZERO at time T The next n pulse occurring at time T will transfer the ONE in core C onto the output line X where it will appear as a ONE corresponding to the P bit position. Also, at time T the ONE in core C is transferred to core C and the P bit which is a ZERO is placed into core C and core C Since core C contained a ZERO and core C contained a ONE at time T the ZERO in core C did not set the core C in the ZERO state.

From the above it is clear that a ONE is always set into core C from either core C or core C as is shown in FIG. 3. Therefore, the bits arriving from the first EXCLUSIVE OR circuit 21 to the core C are always EXCLUSIVE ORed against a ONE bit in the core C This results in the output seen on line X being the ONEs complement of the input to core C as shown in FIG. 3 and disclosed in detail below. Since the number arriving from the memory 28 has already been ONEs complemented by the first EXCLUSIVE OR circuit 21, the second ONEs complementation by the third EXCLUSIVE OR circuit 24 will result in the original number as it arrived from the memory appearing on the output line X as is shown by FIG. 3.

At time T the next (n+1) pulse will EXCLUSIVE OR the ZERO in core C against the ONE in core C thereby setting a ONE in cores C and C Also, at time T the ONE in core C is seen on the output line X as a ONE corresponding to the P bit position, and the ONE in core C is transferred to the core C at the same time that the P bit which is 21 ONE is set into cores C and C At time T the ONE in core C is EXCLUSIVE ORed with the ONE in core C which results in a ZERO set in cores C C and C Also at time T the ONE set in core C is transferred to core C At time T the ZERO in cores C and C is transferred to the output line X where it appears as a ZERO corresponding to the P bit position. Also, at time T the ONE in core C is read out and sets core C in the ONE state at the same time that the P bit, which is a ZERO, is set into cores C and C At time T the ZERO in core C is EXCLUSIVE ORed against the ONE in core C which results in a ONE being set into cores C and C and a ZERO in core C Since the core C was in a ZERO set at time T the core C remains in a ZERO set. At time T the ONE in core C is transferred to the output line X and appears there as a ONE corresponding to the P bit position. Also, at time T the ONE in core C is transferred to core C at the sametime that the P bitpositio-n which is a ONE is set into cores 105 and 123- At' time T the ONEzin core C is EXCLUSIVE ORed against the ONE in core C resulting in a ZERO.

responds to the most significant :bit from the memory' 28 and, as shown above, is the last bit of the number to arrive from the memory 28: Also, as discussed above, the P bit position of the number arriving from the memory 28 is' the sign position bit that indicates the sign of the number. However, the P bit position present in the output of the adder on line X is not used as the sign position bit. The adder will generate a new sign position bit that will occur in the output number immediately after the occurrence of the most significant bit. Therefore, for the present example, the sign; position bit willoccur in the P7 bit immediately after the occurrence of the most significant bit which is in the P bit position. the output was a ZERO which was the sign of the incoming number. However, as will be shown below, when a single negative number is passed through the adder circuit, the P bit position in the output number is also a ZERO.

At time T the ONE in core C will be EXCLUSIVE ORed with the ONE in core C resulting in a ZERO set in-cores C C and C 2 Also, at time T the ONE in core C will be transferred into core C At time T the ZERO in cores C and C will be transferred to the output line X and will appear there as a ZERO corresponding to the P bit position. Also, at time T the ONE in core C is transferred to core C at the same time that a ONE is set into cores C and C due to the ping-pong circuit 27 being on.

As explained above, the new sign position bit is now being generated by the adder. At time T the ONE in core C is EXCLUSIVEORed against the ONE in core C and results in a ZERO set in cores C C and C Also, at time T the ONE in core C is transferred toco're C At time T the ZERO in cores C and C will be transferred to the output line X and will appear there as a ZERO corresponding to the new sign position bit P indicating the number is positive. Also, at time T the ONE in core C is transferred into core C at the same time that a ONE is set into cores C and C due to the ping-pong 27 being on,

It is clear that the adder will contlnue' to give ZEROs in the output positions such as P P P etc., until the ping-pong is turned off because as long as the ping-pong is running, a ONE is always placed into core C and a ONE will always be set into core C from the core C106- The above shows that the adder will pass a positive binary number from the memory 28 unchanged except that the sign position bit is transferred from the P bIlZ position to the next P bit position immediately following the bit position containing the most significant bit. That is, the number entered the adder as:

and left the adder in the form:

As shown above, the P bit positionin 12 It'isobvious that the bit positions-that-occur-on the out.- put, line X prior to'the P bit position (such as bits P P and P and subsequent'to the P bit position (such as bits P P P etc.) are surplu-sage and are to be disregarded. These bits are disregarded by the unit which 7 This may be accomplished in many ways suchias' the use .of timed gates on receives the outputof the adder.

the outputof the adder which are well known in the art. Such arrangements do not constitute any part of the present invention and are not described in detail herein as such arragements are well known in the art.

After the binary number from the memory 28 has passed through the adder unit, it is stored in asuitable storage unit such as the accumulator 29;.

Consider now the case. where a single negative number arrives from the memory 28 to be passed through the adder- FIG. 4 shows the-following number:

of pulses will not be applied to the core C by way of lineX starting at time T Referring now to .FIGS. '2 and 4, at time T the P bit which is a ONE is applied to core C by way ofline X and tends to set that core into the ONE set. However, the STA pulse also occurs at time T and is applied to core C and tends to set that core in the ZERO state. Since the P pulse and the STA pulse tries to set core C into opposite states of remanence, the effect of each pulse will cancel out the other and core C will remaininthe ZERO state. The STA pulse is also applied by way of line X to the core C and sets that core into the ONE state. When the next (n+1) pulse occurs at time T the ZERO in core C will be EXCLUSIVEORid against the ONE:

in core c which will result in a ONE being .set into cores C and C and ZERO in core C At time T the ONE in core C is transferred .to the outputline X and appears there as a ONE corresponding to the P bit position. Also, at time T the ONE in core C1 is transferred to the core C by way of line 34 at the same time that the P bit which a ONE is setinto the core C As shown above,.the STA pulse only occurs once, at time T for each number supplied by the memory 28.

At time T the ONE in core C will be EXCLUSIVE ORd against the ONE in core C which results in a in cores C102, C104 C time .T th ZERO in cores C and C will'be' transferred to the lineX and will appear there as a ZEROcorresponding to the P bit position. Also at time T the P bit, which is 21 ONE, is'set into core C Since there was a ZERO in the core C at time T at ONE was not transferred into core C This diife'rs from the case described above where a single positive number passes-through the adder unit in that when the number was positive there was always a ONE in the core C due to the feedback to core C provided by the core C and by the pulses supplied by the ping-pong 27.

At time T the ONE in core C is EXCLUSIVE iORd against the ZERO in core c which results in a ONEbeing set in core C and a ZERO in cores C and C fed back into core C at time T because there was a ZERO set in core C At time T the ZERO in the core C will be EX- CLUSIVE ORd against the ZERO in core C which results in a ZERO set in cores C C and C At time T the ZERO in cores C and C will be transferred to the line X and will appear there as a ZERO corresponding to the P bit position. Also, at time T the P bit which is a ONE will set core C in the ONE state. A ONE is not present in core C because a ONE was not present in the core C at time T At time T the ONE in core C will be EXCLUSIVE ORd against the ZERO in core C which, as explained previously, will result in a ONE in line X at time T It is apparent now that there can be no ONE set in core C This is due to the fact that 21 ONE is placed into core C and subsequently fed back into core C when and only when a ONE is set in core C and a ZERO is set in core C Since all the remaining incoming bits are placed into core C by way of line X from the memory 28, this condition will never occur.

Therefore, since what is applied to core C will be EXCLUSIVE OR with a ZERO in core C the set of core C will appear unchanged two pulse times later on line X that is, the P bit which is a ZERO and which is set into core C at time T will appear on line X as a ZERO corresponding to the P bit position at time T and the P bit which occurs at time T and is a ONE will set the core C into the ONE state and will appear on line X and time T as a ONE corresponding to the P bit position.

It will be noted that the P sign position bit appearing on line X at time T is a ONE. It was also a ONE when the number arriving from the memory 28 was positive. Therefore, the P bit appearing on line X at time T is always a ONE regardless of whether the incoming number from the memory 28 is positive or negative. Note also that the incoming P bit which occurred at time T is seen as a ZERO on line X at time T and that otherwise the incoming number as it appears on line X was unchanged by the first EXCLUSIVE OR circuit 21, that is, the number arrived from the memory 28 as:

P1 P2 P3 P4 P5 Pa and appeared on line X as:

P1 P2 P3 P4 P5 0 that is, the first least significant ONE bit was ONEs complemented and the remaining bits of the number passed through the first EXCLUSIVE OR circuit 21 unchanged. Had there been any least significant ZERO bits prior to the first significant ONE bit, they would also have been ONEs complemented.

At time T when the P bit was being set into the core C the STA pulse was also applied by way of line X to core C 'and that core into the ONE state. Prior to time T as discussed previously in connection with the positive number from the memory 28, all of the cores are set into the ZERO state prior to the arrival of the P sign position bit from the memory 28. Therefore, at time T the ONE in core C is EXCLUSIVE ORed against the ZERO in cores C and C which results in a ONE being set into cores C and C and a ZERO in core C Since there is no input from the accumulator 29, the cores C C and C can be ignored and the information entering core C from line X will pass through core C unchanged. At time T the ONE in core C will be transferred to the output line X and will appear there as a ONE corresponding to the P bit position. Also, at time T the ONE in core C will be transferred to core C at the same time that the P bit, which is a ONE, arrives on line X and sets a ONE in cores C and C At time T the ONE in core C will be EXCLUSIVE ORed with the ONE in the core C which results in a ZERO set in cores C and C Also, at time T the ONE in core C is transferred to core C At time T the ZERO set of ores C and C is transferred to the output line X and appears there as a ZERO corresponding to the P bit position. Also, at time T the ONE in core C is transferred to core C Since there was a ZERO in core C at time T core C cannot set a ONE into core C As was shown above, in the case of a positive word, a ONE will always be present in core 115 due to the feedback by core C and to the delay means provided by cores C and C Therefore, the bits being placed into core C by Way of line X will always be EXCLUSIVE ORed against a ONE in core C which will result in the complement of the set of core C appearing on output line X two pulse times times later, that is, the P bit which is a ZERO and is set into core C at time T will appear on output line X as a ONE pulse corresponding to the P bit at time T the P bit, which is a ONE, and is set into core C at time T will appear on line X at time T as a ZERO corresponding to the P bit, the P bit which is a ZERO and is set into core C at time T will appear in line X at time T as a ONE corresponding to the P bit, the P bit which is a ONE and is set into core C at time T will appear on line X at time T as a ZERO corresponding to the P "bit, the P bit which is a ZERO and is set into core C at time T will appear on line X at time T as a ONE corresponding to the P bit, and the P bit which is the most significant bit of the incoming number and which, in this case is a ONE and is set in core C at time T will appear on line X at time T as a ZERO corresponding to the P position, as is shown in FIG. 4.

As was discussed earlier, the P bit appearing on the output line X no longer designates the sign of the number. The P bit which occurred on line X at time T is a ZERO which indicates a positive number, whereas, the number passing through the adder is a negative number. The sign position bit will be generated by the adder in the next bit position following the most significant bit which, in this case, is bit P which occurred on the output line X :at time T Therefiore, the sign position bit P will occur on line X at time T and will be a ZERO to indicate that the number passed through the adder from the memory 28 is negative.

Referring now to FIG. 4, it is shown that at time T there was a ONE in core C that was transferred into core C at time T a ONrE is not set into core C because the sign ping-pong 27 is not on and all of the bits of the incoming number have already passed through the first EXCLUSIVE OR circuit 21. Therefore, at time T the ONE in core C is EXCLUSIVE ORed with a ZERO in core C which results in a ONE being set into core C and core C At time T the ONE in core C is transferred to the output line X and appears there as a ONE corresponding to the new sign position bit P which indicates that the number is negative. The adder has, therefore, generated a new sign position bit indicating the sign of the number that is seen on the output line X at time T This is accomplished by there being always a ONE in core C and a ZERO in core C 1 due to the ping-pong not being on at time T The number arrived from the memory 28 in the form:

P0 P1 P2 P3 P4 P5 P0 and appears on line X as:

P7 P1 P2 P3 P4 P5 Pa The answer number seen on line X is the TWOs complement of the number that arrived into the adder from the memory 28. As will be shown below, when the adder performs addition or subtraction and the result 15 is negative, the answer number will appear on line X in the TWOs complement form.

As discussed previously, the excess bits that occur prior to the P position bit, and the excess bits that occur subsequent to the P bit, are disregarded. The bits comprising the output, that is, bits P through 'bits P are stored in a suitable storage means such as the accumulator 29.

Addition of two positive numbers Consider now the case where the adder is to :add two binary numbers. The first number arrives from the memory unit 28 and the second ntunber arrives from the accumulator 29. The number arriving from the memory 28will contain a P sign position bit which indicates its sign, that is, a ZERO if the number is positive and a ONE if it is negative. However, a number arriving from the accumulator 29 does not have a sign P position bit, but rather its sign position bit occurs last, after themcurrence of the bit containing the most significant bit of the number. This was shown above when=1a single number passing through the adder had its sign position bit transferred from the P bit to the bit position following the most significant bit. After'a single number passes through the adder it is stored, until needed, in the accumulator 29.

Assume that the following numbers are to be added as is shown in FIGURE 5 .0 1 1 0 1 from memory .1 1 0 0 0 from accumulator .1 0 0 1 1 answer on line X110 The answer is obviously +.100'l1. It must be remembered. that the P bit position is the least significant bit and the that the P bit position is the most significant bit of the number. The P position bit of the number supplied by the accumulator 29 is. the sign position bit and.

indicates that the number is positive.

Since the number arriving from the memory 28 'is positive the sign ping-pong will be turned on and the number will be ONEs complemented by the first EX-' ulator 29 does not provide a P sign position bit. The

first bit of the number from the accumulator 29 is the P bit and it occurs at time T and is applied to core C by way of line X Core C delays the word arriving from the accumulator 29 by onepulse time so that the bits j of the number from the accumulator 29 entering the core appears on line X beginning at time T and the output from the first EXCLUSIVE OR circuit '21 that appears on line X beginning at time T Cores C C C and C comprise the second EXCLUSIVE OR circuit 23 shown in block diagram form in FIG. 1. The output from thefirst EXCLUSIVE OR circuit 21 appears on line X and is EXCLUSIVE ORed with the output of core. C which appears on line X which. appears online X As is shown in FIG. ,5, the ONEs complement of the number arriving from the 16 V 7 memory 28*appears on line X and is EXCLUSIVE. ORed with the outputrof coreC which is the number arriving from the accumulator29. and which appears on line X103.

FIGS; 2 and 5 show that at time.T ,-.the STA pulse is applied by way of line X1 to core C and sets that coreinto the ONE state., At time T the ONE in core C is EXCLUSIVE ORed with the ZERO in core C which results in 21 ONE being set into cores C and C and a ZERO set in core Cm. At timeT the ONE in core C is transferred to the outputyline X' and appears there as a ONE'corresponding to the P bit position. Also, at

time T the ONE in coreCm is transferred to the. core C 1 at the same .timethat the -P o'bit, WhlChjiS a ONE, enters cores C and C The. P bit which was: entered j into cores C and C at.time T is the P sign position bit of, the number arriving into the adder from the 9 memory 28.and, as has been shown previously, it is,

always a ONEiwhen it. arrives on line X from first EXCLUSIVE OR circuit 21.

At time T7, the ONE: in core C is EXCLUSIVE ORed against the ONE in core C which results in a ZERO set in coresC C and C Also at time T .the ONE in the core Q is transferred into core C Attime T the ZERO.in:cores C and C 1 will be trans-: ferred to the output line X and will appear there as a j ZERO corresponding to the P bit position. Also, at time. T the. ONE in core C 0 is transferred into core Notice that at time T the P bit position of the number arriving from the memory v2.8 is appearing on line X and also that theP bit position of'the word arriving from the accumulator 29 is. arriving on line X Since cores C C C and C comprise the now familiar.

EXCLUSIVE OR circuits; these bits arriving on these two lines will be EXCLUSIVE ORedagainst each other. Reference to FIG. 5 shows that'at time T ,]the P bit position arriving on line X is a ONE and will be EX- CLUSIVEORed against the P 1 bit position appearing on line X which is also a ONE which will result in a ZERO set in the cores C C1 andC Attime T the ONE.

and is EXCLUSIVE ORed against-the P 'bit position of the number arriving from the accumulator =29,'which appears on line X' as 3. ONE; resulting in a ONEiset in core C and a ZERO set invcores C and C1 At time T the 'ONEin'core C is EXCLUSIVE ORedagainst the ONE in core C resultingin a ZERO set in cores C C and C At' timeT the ZERO'in cores C anclC istransferred to' the output line X where a ZERO will appear'corresponding to the P bit position. Note that 'a ONE was nottransferred into core C from eithercore C 'or C124; at the time T This is in contrast to the condition when a single number from the memory28 passes through the adder'in whichjcase a ONE is always present in the core C 7 At time T thePg bit position of theo word arriving from the memory appears on lineX It is a ZERO, and is EXCLUSIVE ORed with thecorresponding P bit position of the word arriving from the-accumu1ator,29,= which is a ZERO appearing on line X' r The EX".

CLUSIVE ORing results in a ZERO in cores C C 5 and'C Attime T the ZERO in cores C and C will be EXCLUSIVE ORed againstthe ZERO in core- C which will result in ZEROs in cores C C 1 and C and a ZERO on the output line X 1 at time T ,correspondingto the P bit position.

"ZERO bit.

At time T the P bit seen on line X is a ONE and is EXCLUSIVE ORed with the P bit seen on line X which is a ZERO resulting in a ONE set in cores C and C Since there was not a ONE in core C or core C at time T there will not be a ONE set in core C at time T14. At time T15, the in core C105 IS ORed with the ZERO in core C resulting in a ONE in core C and a ZERO set in cores C and C Also, 'at time T15, the ONE in core C will be transferred to the core C At time T the ONE in core C will be transferred to the output line X and will appear there as a ONE corresponding to the P bit position. Also, at time T the ONE in core C will be transferred to core 115.

At time T the P bit position seen on line X is a ZERO and is EXCLUSIVE ORed with the P bit position seen on line X which is a ZERO which results in a ZERO set in cores C C and C It should be noted that the P bit position is the most significant bit position of the two binary numbers being added by the adder. As discussed above, the adder will generate a sign position bit that indicates the sign of the number on the output line X in the next bit position following the most significant bit. In this case, since the most significant bit of the numbers occurs in the P position, the P bit occurring on the output line X will contain the sign of the result of the addition performed by the adder. Since the result of the addition being performed by the adder is positive, the P position appearing on line X at time T must be a ZERO. At time T the ZERO in cores C and C will be EXCLUSIVE ORed with the ONE in core C resulting in a ONE in cores C and C and a ZERO in core C At time T the ONE in core C will be transferred to the output line X and will appear there as 2. ONE corresponding to the P bit position. Also, at time T the ONE in core C will be transferred to core 11s- Now the adder must give a P bit position that indicates that the result of the addition appearing on line X is positive, that is, the adder must generate a P At time T a ZERO appears on line X corresponding to the P bit position indicating the word arriving from the accumulator 29 was positive. Also, a ONE will appear on line X at timeT because the ping-pong is running which is EXCLUSIVE ORed with the ZERO on line X Therefore, at time T a ONE appears in cores C and C At time T the ONE in core C is EXCLUSIVE ORed against the ONE appearing in core C which results in a ZERO in cores C110, C116 and C124. time T20, the in COI'CS C and C is transferred to the output line X and appears there as a ZERO corresponding to the new sign position bit P and indicates that the result of the addition of the two numbers is positive. Also, at time T the ONE in core C is transferred to core C The above shows that the number arriving from the adder is:

Pa P1 P2 P3 4 P5 Addition of a negative and positive number Consider now the case when the number arriving from the memory 28 is negative and is -.l0l10 and the number arriving from the accumulator 2-9 is positive and is +.000l1 as is shown in FIG. 6. The result is obviously -.100l1. Since a negative number always leaves the adder in TWOs complement form, the answer from the 18 adder will be the TWOs complement of .00011 which is .0'1'l01. The input numbers and the result will enter and leave the adder in the following form:

P1 2 P3 P4 5 0 1 1 0 0 0 0 fromaccumulator 29 The P bit of the number arriving from the memory 28 is the sign position bit and indicates the sign of the number. The P bit is the sign position bit of the number arriving from the accumulator 29 and indicates that the number is positive. The P bit is also the sign position bit of the answer and indicates that the answer is negative. The P bit is the least significant and P is the most significant bit of both of the numbers. Since the number arriving from the memory 28 is negative, the sign ping-pong 27 will not be activated. Also, because the number is negative, it will appear on line X which is the output of the first EXCLUSIVE OR circuit 21, with the first least significant ONE and all lower order ZEROs complemented. That is, the number arriving from the memory 28 will appear on line X as:

from memory 28 1 answer on line X110 with the ZEROs in cores C and C which results in a ONE in cores C and C is transferred to the output line X where it appears as a ONE corresponding of the P bit position. Also, at time T the ONE in core C is transferred to core C by way of line 35 at the same time that the P bit of the number from the memory 28, which is a ONE, arrives on line X and sets a ONE in cores C and C At time T the ONE in core C is EXCLUSIVE ORed with the ONE in core C which results in a ZERO set in cores C C and C Also, at time T7, the ONE in core C is transferred to core C At time T the ZERO in cores C and C is transferred to the output line X and appears there as a ZERO corresponding to the P bit position. Also, at time T the ONE in core C is transferred into core C At time T the first P bit of the number arriving from the memory 28 appears on line X after being passed through the first EXCLUSIVE O-R circuit 21 and is EXCLUSIVE ORed with the first P bit of the number arriving from the accumulator 29 which appears on line X Core C acts as a delay causing the bits of the number arriving from the accumulator 29 to appear on line X at the same time as the corresponding bits of the number from the memory 28 appear on line At time T the P bit on line X is a ONE and is EXCLUSIVE ORed with the P bit on line X which is also a ONE resulting in a ZERO set in cores C C and C At time T the ONE in core C is EXCLUSIVE ORed with the ZERO set of cores C and C resulting in a ONE set in cores C and C At time T the ONE in core C is transferred to the output line X and appears there as a ONE corresponding to the P bit position. Also, at time T the ONE in core C is set into core C At time T the P bit on line X is a ZERO and is EXCLUSIVE ORed with the P bit on line X which is a ONE resulting in a ONE set in core C and a ZERO set in cores C and C At time T the ONE in core C is EXCLUSIVE ORed with the ONE in core C resulting in a ZERO set in cores C C and C At time T the ZERO set of cores C and ONE incore C is EXCLUSIVE ORed against the ZERO in core C resulting in a ONE set-in core C and a ZERO set in cores C and C 2 Also, at time T the ONE in core C 'is transferred into core C At time T the ONE in core C is transferredto the. output line X where it appears as a O NE corresponding to the P bit position. Also, at time T the ONE in core C is transferred to core C At time T the P bit on line X1 is a ZERO and is EXCLUSIVE ORed against the P bit on line X which is also a ZERO resulting in a ZERO set in cores C C and C109. time T15, the in core C115 is CLUSIVE ORed against the ZERO in cores C and C resulting in a ONE set in cores C and C and a ZERO set in core C At time T the ONE in core C is transferred to the outputline X where it appears as a ZERO corresponding to the P bit position. Also, at time T the one in core C is transferred into core 115- At time T the P bit on line X is 21 ONE and-is EXCLUSIVE ORed against the P bit on line X which is a ZERO resulting in a ONE set in cores C1o5.'and C and a ZERO set in core C At time T the ONE in core C is EXCLUSIVE ORed against the ONEin core C resulting in a ZERO set in cores C C and C 4. Also, at time T the ONE set of core C is transferred to core C At time T the ZERO set of cores C and C is transferred to the output line X where it appears as a ZERO corresponding to the P bit position. Also, at time T the ONE in core C is set into core 115- It will be noted that all of the bits of both numbers have now passed through the adder and now the adder must generate the sign bit for the answer number. At time T the bit seen on line X is a ZERO, because the sign ping-pong is not turned on by a negative number arriving from the memory 28, which is EXCLUSIVE ORed against the P sign bit position on line X which is a ZERO resulting in a ZERO set in cores C C and C The P bit on the number arriving from the accumulator 29 is the sign position bit of that number as explained previously and is a ZERO. because the number is positive. At time T the ONE in core C is EX- CLUSIVE ORed against the ZERO in cores C and C resulting in a ONE set in cores C and C and a ZERO set in core C At time T the ONE in core C is transferred to the output line X where it appears as 21 ONE corresponding to the sign. position bit P Reference to FIG. 6 will show that the answer appearing on line X is the TWOs complement of the correct answer and that the adder has generated the correct sign of the resulting addition in the P bit position. The answer comprises bits P through P viously, all other bits appearing on the output line X will be disregarded.

The operation described in conjunction with FIG. 2 show that core C comprises a part of the first EX- CLUSIVE OR circuit 21 and part of the second EX- CLUSIVE OR circuit 23. Cores C and C comprise part of the second EXCLUSIVE OR circuit 23 and also a part of the third EXCLUSIVE OR circuit 24. This arrangement reduces the number of magnetic cores used in the adder circuit. Also, it is' clear that the delay provided by cores C and C is essentially a carry operation. FIG. 2 also shows that the core C is part of the inhibitor circuit 25. and part of the fourth'EXCLUSIVE OR circuit 26. i

As explained pre- I iS'u btraciu'ort Since the addition. of: .a negative number to a positive number is subtraction, it is evidentjhat the adder can 2 In order tohiperform' subtraction, the adder must first determine. the sign. That is, if the 1 perform subtraction.

subtrahend is; a negative number, the resulting subtraction becomes a straight addition and if the subtrahend .is,

a positive number, the resulting subtraction is the addi tion of the complement of the: subtrahenda The sign isdetermined by the inhibitor circuit 25 and the fourthiEXCLUSIVE OR circuit 26. I Referring now to FIG. 2,. at time T the P 'bit, of the word arriving from the memory 28, isl'placed into core C The STA pulse also occurs attimeT, at terminal 30 andsetscore C in the ONEi-state. If the operation to be performed is subtraction, an ,SUA. pulse occurs on terminal 31 at time T and will set core C into the ONE state. Attime T the next. (n+1) pulsewill advance all threecores: C C and C However, if P is a ONE,-it

will inhibit the ONE in core. c from being set into core 1 C If P wasa ZERO, :the .ONE in core C will be set into core C as was described previously.- In either case, at time T the next it pulse advances the set of cores C and: C into the fourth EXCLUSIVE OR circuit comprising cores C C C and C Thus,,if the number is negative, i.e., P is a ONE,: then core C is set into the ONE state. However, if the number is positive, i.e., P is a ZERO, neither core C or core C will be set into the ONE;state. At time T the next (n+1) pulse will read out cores C and C and ac.- tivate the ping-pong if the word was negative. After the sign is determined, the adder goes on toperform' addition as described above.

Cores C C and C formthe circuit used for subtraction by determining the sign of theincoming word and the operation to be performed as shown in the following table:

Operation SUA STA Po Ping-Pong 0 1 0 ON at Ta. 0 1 1 OFF. 1 1 1 ON at Ts. Subtract 1 1 0 OFF.

The table shows that whenever any: two of these inputs (STA, SUAor P5 are a ONE) the sign ping-pong is OFF, otherwise the sign ping-pong will be activated.-

Since any mathematical operation may be defined in terms of addition and subtraction, it is clear that by proper programming, .the adder may perform many mathematical operations.

Rounding. ofl

The adder can also round off the resulting answer for certain operations. In any operationbut addition and subtraction, the number of bits in the result may be more generated at time T, on terminal 33 asshown in FIG. 2

and applied by way of line X to cores C C and C It was shown: previously, that the P bit of the number arriving from the memory 28 or accumulator 29 will appear on line X or line X attime T The extra bits P P etc., occur prior to time T Therefore, cores C and C may or may not have a ONE set at time T when the P bits arrive. At time T the RDA pulse appearing on terminal 33 is applied to cores C C and C by way of line X The RDA pulse sets a ZERO into cores C and C and a ONE in core C Also, at time T the STA pulse sets core C into the ONE state.

At time T the ZERO in core C is advanced to core C At the same time, the ONE in core C is EX CLUSIVE ORed against the ONE in core C resulting in a ZERO set in cores C C and C That is, neither core C nor core C is set with a ONE at time T At time T the ZERO set of cores C and C is transferred to the output line X and appears there as a ZERO corresponding to the P bit position. Also, at time T a ONE is not transferred into core C because cores C and C contained ZEROs. Reference to FIGS. 3, 4, 5 and 6 show that the P bit position is always a ZERO.

Further, at time T the P bit arrives on line X and, as shown above, is always a ONE and it will be the only determining bit for rounding off the result of an adder operation. Thus, the word has been rounded off, i.e., no ONE bits can occur in the output prior to the P bit, and only the first bit on the least significant side of the P bit is the determining factor in the round off.

Clearing the adder For most operations performed by the adder, clearing of the adder is accomplished by the n and (n+1) pulses advancing any left over bits out of the adder circuits prior to the arrival of new incoming numbers. This is possible because of the serial input nature of the incoming bits. However, in some cases, it may be desirable to clear the adder quickly without waiting for the left over blts to be pulsed out of the adder. This can be accomplished by the CL pulse. Reference to FIG. 2 will show that each core contains a CL input winding that will set the core into the ZERO state. Whenever it is desirable to clear the adder quickly, the CL pulse is generated and applied to all of the cores simultaneously which sets each core into the ZERO state.

Also, once the ping-pong has been started, it is necessary that it be turned off prior to the beginning of the next operation to be performed by the adder circuit. 7 It is obvious that the CL pulse will deactivate the ping-pong because the CL pulse will simultaneously set a ZERO into cores C and C which comprise the ping-pong circuit 27. However, when the CL pulse is not used to clear the adder, the STA pulse occurring for the next operation will deactivate the ping-pong 27.

' Assume the adder performed an operation which activated the ping-pong circuit 27. The ping-pong 27 will continue running after the operation is completed. When the next operation to be performed by the adder is to begin at a time corresponding to T the STA pulse is generated, and as is shown in FIG. 2, is applied to core C of the ping-pong and sets the core into the ZERO state. The double arrowhead on the STA input line to core C indicates that the existence of the STA pulse will hold the core C to that state despite the presence of other input signals. Reference to FIG. 3 will show that if' the pingpong is running, the ONE in core C will be transferred into core C at all even numbered pulse times. Therefore, the ONE from core C will appear as an input to core C at the same time that the STA pulse is applied to core C However, because of the nature of the STA input winding discussed above, the ONE from core C will not set a ONE in core C but the STA pulse will keep core C in a ZERO set. Therefore, at the time equivalent to time T when the next operation begins, a ZERO will be in cores C and C comprising the pingpong 27 and the ping-pong 27 will be deactivated.

Note that at the time equivalent to time T the ONE pulse from core C is also applied by line X to core C and tends to set that core in the ONE state. This is not undesirable because the STA pulse which occurs at the same time is also applied to core C and tends to set it into the ONE state. That is, it is necessary that a ONE be set into core C at the time equivalent to time T for every operation performed by the adder.

Sign determination It was shown previously in the detailed description of functions performed by the adder, that the adder circuit generates a bit which indicates the sign of the number leaving the adder and that this sign bit occurred in the next bit that occurs subsequent to the most significant bit of the number leaving the adder. No one particular circuit in the adder determines the sign bit. Rather, it is a function of (a) whether the ping-pong 27 was turned on, (b) the sign of the number supplied by the accumulator 29, and (c) the internal condition of core C at the time the sign position bit is generated. The rules for sign determination of the output of the adder are:

(1) When two positive numbers are added; at the same time that a ONE pulse is set into core C due to the ping-pong 27 circuit being on a ONE pulse is set into core C from either core C10 'Ol' C When the ONE in core C is EXCLUSIVE ORed against the ONE in core C it produces a ZERO in the sign position bit of the output.

(2) When two negative numbers are added; at the same time that the sign position ONE bit of the number from the accumulator 29 is placed into core C a ONE pulse is not placed into core C from either core C or C When the ONE in core C is EXCLUSIVE ORed with the ZERO in core C it produces a ONE in the sign position bit of the output.

(3) When two numbers are added, one positive and one negative, and the positive number is the greater and arrives from the memory 28; at the same time that a ZERO is placed into cores C and C due to the pingpong 27 being on and a sign position ONE pulse arriving from the number supplied by the accumulator 29, a ONE pulse is not placed into core C from either core c or C When the ZERO in cores C and C is EX- CLUSIVE ORed with the ZERO in core C it produces a ZERO in the sign position bit of the output. I

' (4) When two numbers are added one positive and one negative, and the positive number is greater and arrives from the accumulator 29; at the same time that a ZERO is placed into cores C and C due to the pingpong circuit 27 not being on and a ZERO in the sign position bit of the number supplied by the accumulator 29, a ONE pulse is not placed into core C either from core C or core C When the ZERO incoreC and C is EXCLUSIVE ORed against the ZERO in core C it produces a ZERO in the sign position bit of the output.

(5) When two numbers are added, one positive and one negative, and the negative number is greater and arrives from either the memory 28 or accumulator 29; at the same time that a sign position ZERO i placed into cores C and C in accordance with'Rules 3 and 4 above, a ONE is placed into core C from either core C106 01' C124. When the in cores C105 and C109 IS EXCLUSIVE ORed with the ONE in core C it produces a ONE in the sign position bit of the output.

The validity of Rules 1 and 5, respectively, has been shown previously by the detailed description of addition by the adder in connection with FIGS. 5 and 6. FIG. 9 shows in tabular form the set (remanent state) of the cores for each time step for the addition of two negative numbers as stated in Rule 2. It is not necessary here to describe in detail the state of each core for each time period because the reader may do this himself after a reading of the detailed description given previously. Note that since the number from the accumulator 29 is negative it will be in TWOs complement form and since the answer is negative, the answer will also be in TWOs complement form. a r

the numbers have passed through the adder and a ZERO appears on line X because the ping-pong circuit is not activated. The ZERO on line X is EXCLUSIVE ORed against the ONE occurring on line X which is the P sign bit of the number supplied by the accumulator 29, resulting in a ONE set in core C and a ZERO set in cores C and C Also, at time T a ZERO is in core C because there was not a one in either core C or C at time. T Attime T 1, the .ONE in core C is EXCLUSIVE ORed against the ZERO in core C resulting in a ONE set in core C and a ZERO in cores C115 and C124. At time T22, the in core C110 IS transferred to the output line X and appears there as.

a ONE corresponding to the sign position bit P Therefore, the validity of Rule 2 has been shown.

FIG. 8 shows in tabular form the state of the cores.

greater and arrives from the memory 28 as stated-in Rule 3. Reference to FIGS. 8 and :2will show that at time:

T the bits (P to P of the numbers being added have passed through the adder. A ONE appears on line X at time T because the ping-pong is activated, which is EXCLUSIVE ORed against the sign position bit P of the number supplied by the accumulator 29 appearing on line X which is a ONE, resulting in a ZERO set in cores C C and C At time T a ONE is not set into core C because at time T a ZERO set was in cores C and C At time T the ZERO in cores C and C is EXCLUSIVE ORed against the ZERO in core C resulting in a ZERO set incores C C and C At time T the ZERO set of cores C and C is'transferredto the output line X where is appears as a ZERO corresponding to the sign position bit P Therefore, Rule 3 is validated.

v FIG. 7 shows the set of the cores when a positive and negative number are added, and the positive number ar- 1 rives from the accumulator 28, as stated in Rule 4.

Reference to FIGS. 2 and 7 will show that at time T the bits (P to P of the two nurnbers have. passed through the adder. At time T a ZERO appears on line X because the ping-pong was not turnedon, which is EX-' CLUSIVE ORed against the sign position bit P; on line X10g'WhiCh is a ZERO because the number from the accumulator 29 is positive, resulting in a ZERO set in cores C C and C At time T a ZERO set is in core C because a ZERO set was in'cores C and C at time T as shown in FIG. 7. At time T theZERO in cores C and C is EXCLUSIVE ORed against the ZERO in core C resulting ina ZERO in cores C 1 stated in Rule 5. Reference to FIGS. '10 and 2 will show,

that at time T the bits (P to P of both numbers have passed through the adder. At time T20, a ONE appears on line.X because the ping-pong was activated, and is EXCLUSIVE ORed against the sign posi-.

tive bit P of the number supplied by the memory 29,

which is a ONE because the number is negative, result ing in a ZERO set in cores C C and C Refer ence to FIG. 10 shows that core C contained a ONE at time T which is transferred into core C at time T At time T the ZERO in cores C and C is EXCLUSIVE ORed against the O'NEin core C resulting in a ONE in cores C and C and a ZERO in core C At timeT the ONE in core C is transferred to the output line X1 where it appears as a ONE corresponding "to the sign position bit P as is shown in' FIG. 10.. Therefore, Rule 5 has been shown to be valid. 7

The rules given above are only 'valid when there is notan overflow, i.e., when neither-of'theinput numbers nor the answer. appearing on;line X is greater than unity. As was: explained previously, the adder cannot handlea number greater than unity.

The inhibitor circuit FIG. .11 shows in symbolic form and FIG. 111A shows in schemati-c.form the inhibitor; circuit used in the algebraic adder. Reference .to FIG. 11 shows the inhibitor circuitcornprises three magnetici cores C C 1 and C each having'a substantially rectangularxhysteresis loop characteristic. There are two inputs (STA' pulse and memory, 28) and a single output-X FIG. 11A shows that a split-winding circuit interconnects-core C to cores C and C 5 The'dots. shown near the windings in FIG. 11A indicate that current 'intoa dot terminal will set the core into the ZERO Istate. Conversely, a

current flowing rout of a dotterminal, sets the core into the;ONEz state..- FIG. 11A shows that an STA "pulse applied to windings 201 set core C into the: ONE 1state,- and a pulse arriving from the memory 28 applied to the windings203 will set core-C into the ONE state,

A ONE in core Core C inhibits'the transfer ofa ONE from core C to C Assume that there is a ONEin;

cores C and C12 The transfer pulse (n+1) is ap:

plied to terminal 208 :creating a current I (n+1) which divides into lines 210 and 211 as currents I and I respectively. Because a ONE is in both cores C and C the impedance presented. by winding 202 of core. C to the current I ?is equal to the impedance presented by windings 204 of core C 5 to the current@I ,Therefore, current'l isfequal to current I Accordingly, the magnetizing force produced by current I passing through the winding 206 on core C tending to switch the core cm into the ONEstate is canceled by an equal and opposite magnetizing force produced by the equal current I passing throughthe winding 205 on core C that tends to switch the core C into the ZERO: state.

If a core is in the: ZERO state and a current is applied to'a winding that tends to switch the core into the ONE state, a large counter E.'M.F.- will :be. generated in the winding and the core willlook like a relatively high impedance to the. driving source. However, if the core is already in the ONE state when the current is applied, the

counter will be small and thecore will appear;

almost as a short circuit to the driving source.

Assume now that a ONE is in core C of FIG. 11A

and'a ZERO is-in;core C When the advance pulse (n+1) is applied to the terminal 208, the: current 1 tends to switch core 0 into theZERO state. However, since core C is already in the ZERO state, the impedance presented by'the winding 204 to the current I will be vvery small. Thecurrent'l tends to switch core .C

into the ZERO state and since core C is in the ONE state the impedance presented by the windings 202 to the current'l will be very large, as explained above. Since the windings 202 of core C present a much higher impedance than the windings 204 of core C to the flow of current, the current I will be much larger than the current I Therefore, the magnetic flux created by winding 206 of core C due to the current I and which tends to switch core C into the ONEstate will bemuch larger than the magnetic flux created-by the current I flowing through the .winding205 of core. C which.

tends to switch the core C into the ZERO state, Consequently, core C11 will beset into the ONE'state. That.

25 The diodes 207 and 208 shown in FIG[ 11A prevent current flow in lines 211 and 210 when information is read out of core C into the output (not shown in FIG.

11A). This inhibitor circuit is described in the February 1956 issue of the Proceeding of the IRE on pages 154 to The pzng-pong czrcuzt The ping-pong circuit is shown in symbolic diagram form in FIG. 12 and in schematic diagram form in FIG. 12A. Reference to these figures will show that the pingpong circuit comprises two magnetic cores of substantially rectangular hysteresis loop characteristics C and C An input to the windings 215 of the core C set that core into the ONE state. The n transfer pulse is applied to the windings 214 of the core C and will switch the core C back to the ZERO state. When this occurs, an output pulse is generated on the output winding 213, passes through the diode 220, and is seen as the output of the ping-pong. Also, the switching of core C from the ONE into the ZERO state by the n transfer pulse, induces a current in the loop 218 that passes through the diode 217 and sets the core C into the ONE state.

The next (n+1) transfer pulse to occur is applied to winding 212 of the core C and will switch that core into the ZERO state. When core C is switched into the ZERO state, a current is induced in the 'loop 219 that passes through diode 216 and sets the core C into the ONE state. The n and (n+1) transfer pulses will continue this transferring of a ONE back and forth between cores C and C until the ping-pong circuit is turned off. As explained previously, the ping-pong can be turned off by simultaneously applying a pulse to a winding (not shown) on each core C and C that will simultaneously set a ZERO in each of the cores.

The EXCLUSIVE OR circuits FIG. 13 shows in symbolic form, and FIG. 13A shows in schematic diagram form, the EXCLUSIVE OR circuits utilized in the adder as the second 23 and fourth 26 EXCLUSIVE OR circuits. An input pulse on winding 221 of the core C shown in FIG. 13A sets that core into the ONE state and an input pulse on winding 223 of the core C sets that core into the ONE state. Assume that a ONE is set in core C and a ZERO in the core C The next n transfer pulse that occurs is applied to the terminal 229 which creates a current I The I current divides into an I current in line 231 and 1;, current in line 232. The I current passes through the windings 222 of the core C and tends to switch the core C from the ONE state into the ZERO state. Since core C is already in the ZERO state, the windings 224 will represent :a very small impedance to the flow of the current I Because the line 232 represents a smaller impedance to the flow of current than the line 231, the I current will be larger than the I current. The larger I current flows through windings 226 and generates a magnetic flux in core C that tends to place that core in the ZERO state. The smaller I current flows through the windings 225 and generates a magnetic flux that tends to place the core C into the ONE state. However, since the I current is larger than the I current, the magnetic flux created by the I current will be larger than the magnetic flux created by the I current and core C will remain in the ZERO state.

The larger I current also flows through windings 228 and generates a magnetic flux in core C that tends to place that core into the ONE state. The smaller 1 current flows through windings 227 and generates a smaller magnetic flux that tends to set a ZERO in core C Since the magnetic flux created by the I current is larger, the core C is switched into the ONE state. That is, the ONE in core C has been transferred to the core C From the above, it is obvious that had the ONE set been in core C and a ZERO in core C the current I would be larger than the current I resulting in a ONE 26 in the core C and a ZERO in core C If a ONE set is in both cores C and C the I current will be equal to the I current and there will be no change in the set of either core c or C The I current will also be equal to the I current when a ZERO set is in cores C and C113.

The output windings (not shown) of the cores C and C are tied together and each core is read out by a transfer pulse (not shown) simultaneously.

FIGS. 14 and 14A show an EXCLUSIVE OR circuit having a feedback core C in a feedback loop 34. This circuit is used as the first 21 and third 24 EXCLUSIVE OR circuits in the algebraic adder. Reference to FIG. 14A will show that, except for the extra core C and the feedback loop 34, the circuit is identical to circuit shown in FIG. 13A. Note that the windings 241 and 242 of the feedback core C are identical to the windings 239 and 240 on core C Therefore, a ONE or a ZERO will be set into core C whenever a ONE or a ZERO is set into the core C That is, the set of cores C and C 'will always be the same. Accordingly, when a ONE appears in core C and a ZERO in core C a ONE will be transferred into cores C and C and a ZERO into core C by the transfer pulse (n+1). Conversely, when a ONE is in the core C and a ZERO in the core C the next (n+1) pulse applied to terminal 251 will result in a ONE in the core C and a ZERO set in the cores C and C The output windings (not shown) of cores C and C are tied together and each core is read out simultaneously by a transfer pulse (not shown). At the same time that cores C and C are being read out, the same transfer pulse (not shown) is applied to the core C and if core C contained a ONE set, it will be switched into the ZERO state which induces a current I, in the feedback loop 34 that sets a ONE into the core C Otherwise, the operation of the EXCLUSIVE OR circuit shown in FIG. 14A is the same as the EXCLUSIVE OR circuit shown in FIG. 13A. The EXCLUSIVE OR circuit shown in FIG. 13 is described in detail in the February 6 issue of Proceedings of the IRE, pages 154 to 162.

The detailed description given above shows that high reliability magnetic core circuits may be combined to form an algebraic adder that uses a minimum number of such magnetic cores resulting in even greater reliability. It has been shown that the adder circuit gives the sign value of the output and also rounds ofi the output number. The number of magnetic cores needed in the circuit is minimized by overlapping the functions performed by certain cores.

What is claimed is:

1. A binary algebraic adder comprising: at least a first and second source of binary numbers, sign determining means adapted to receive and determine the sign of said first source of numbers, first means coupled to said first source of numbers and said sign determining means and adapted to provide an output which is the result of ones complementing the first least significant ON-E bit and all lower order ZEROS of a negative number supplied by saidfirst source of'numb'ers and further adapted to provide an output which is the ones complement of a positive number supplied by said first source of numbers, and second means adapted to receive said second source of numbers and said output of said first means for adding the numbers supplied by said second source of numbers to said output of said firstmeans.

2. A binary algebraic adder comprising: a first and second source of binary numbers, magnetic core sign determining means adapted to receive and'determine the sign of said firstsource of numbers, first magnetic core 'means coupled to said first source of numbers and said 'sign determining means and adapted to provide an output which is the result of ones complementing the first least significant ONE bit and all lower order ZEROS of a negative number supplied by said first source of numbers and 

3. A SERIAL BINARY ADDER CIRCUIT COMPRISING: A FIRST AND SECOND SOURCE OF BINARY NUNBERS; SIGN DETERMINING MEANS ADAPTED TO RECEIVE AND DETERMINED THE SIGN OF THE NUMBERS SUPPLIED BY SAID FIRST SOURCE NUMBERS; COMPLEMENTING MEANS COUPLED TO SAID FIRST SOURCE OF NUMBERS AND TO SAID SIGN DETERMINING MEANS AND ADAPTED TO PROVIDE AN OUTPUT BINARY NUMBER WHICH IS THE NUMBER SUPPLIED BY SAID FIRST SOURCE OF NUMBERS BUT WITH THE FIRST LEAST SIGNIFICANT ONE BIT AND ALL LOWER ORDER ZEROS ONE''S COMPLEMENTED WHEN THE NUMBER IS NEGATIVE AND ADAPTED TO PROVIDE AN OUTPUT THAT IS THE ONE''S COMPLEMENT WHEN THE NUMBER SUPPLIED BY SAID FIRST SOURCE IS POSITIVE; A FIRST EXCLUSIVE OR CIRCUIT HAVING A FIRST INPUT COUPLED TO THE OUTPUT OF SAID COMPLEMENTING MEANS, A SECOND INPUT COUPLED TO SAID SECOND SOURCE OF BINARY A SECOND INPUT HAVING AN OUTPUT; A SECOND EXCLUSIVE OR CIRCUIT HAVING A FIRST INPUT COUPLED TO THE OUTPUT OF SAID FIRST EXCLUSIVE OR CIRCUIT, A SECOND INPUT AND AN OUTPUT; AND DELAY MEANS COUPLED BETWEEN THE OUTPUT OF SAID COMPLEMENTING MEANS AND THE SECOND INPUT OF SAID SECOND EXCLUSIVE OR CIRCUIT; SAID FIRST AND SECOND EXCLUSIVE OR CIRCUITS AND SAID DELAY MEANS ADAPTED TO ADD THE BINARY NUMBERS SUPPLIED BY SAID SECOND SOURCE OF NUMBERS TO THE OUTPUT OF SAID COMPLEMENTING MEANS SUCH THAT THE SUM OR DIFFERENCE OF THE NUMBERS PROVIDED BY THE FIRST AND SECOND SOURCE OF NUMBERS APPEARS ON THE OUTPUT OF SAID EXCLUSIVE OR CIRCUIT. 